A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2016 PROJECT TITLE : A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2016 ABSTRACT: In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor primarily based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba-Ofman methodology to realize high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, that results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs single-purpose multiplication using points in affine coordinates in 2.twenty six ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Field Programmable Gate Arrays Logic Design Application Specific Integrated Circuits Public Key Cryptography Instruction Sets A Mixed-Decimation MDF Architecturefor Radix-2k Parallel FFT - 2016 A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling - 2016
