PROJECT TITLE :
Speculative Look ahead for Energy-Efficient Microprocessors - 2016
In addition to being the in situ performance monitor for adaptive voltage scaling (AVS), timing speculation mechanisms (e.g., razor) that includes dynamic timing fault detection and correction facilitate to relax timing constraints for easy logic structures and low-power cells. Standard timing fault detection mechanisms require substantial buffers to forestall race conditions on short methods for double sampling, which can overwhelm energy savings from timing relaxation and voltage scaling. This paper proposes a completely unique timing speculation scheme, speculative lookahead (SL), comprising duplicate timing-relaxed datapaths, the short ways of which don't introduce race conditions and so require no additional buffer insertion. In experiments employing a forty-nm CMOS technology, SL consumed a 54.eighty ninepercent area of a razor-based mostly thirty two-bit multiplier, and conserved 59.77p.c energy per operation at nominal 1.one V and fifty three.49% when AVS was applied. An ARM Cortex M0-like microprocessor unit (MPU) was designed using an SL-based datapath, the timing fault detection and correction mechanism of that will be dynamically deactivated for latency-tolerant instructions [i.e., on-demand timing speculation (ODTS)] to additional conserve up to 31.08% energy within the execution unit. Additionally, an field-programmable gate array prototype of the SL/ODTS MPU was made to demonstrate the effectiveness of delay variation tolerance and implementation flexibility.
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