Efficient Synchronization for Distributed Embedded Multiprocessors - 2016


In multiprocessor systems, low-latency synchronization is extremely important to effectively exploit fine-grain information parallelism and improve overall performance. This temporary presents an efficient synchronization for embedded distributed multiprocessors. The proposed answer works during a completely decentralized request-response manner via specific message exchange among the processing elements. Scalable lock and barrier synchronization algorithms, that are derived from the inherent distributed characteristics of the underlying design, are proposed to enable fair, orderly, and rivalry-free synchronization. We tend to implement the proposed synchronization model in a distributed 32-core architecture with a business cycle-correct SystemC simulation platform. Experimental results that show our proposed approach achieves ultralow synchronization latency and nearly ideal scalability when the core count scales.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE :Efficient Secure Outsourcing of Large-Scale Sparse Linear Systems of Equations - 2018ABSTRACT:Solving large-scale sparse linear systems of equations (SLSEs) is one in all the foremost common and basic problems in
PROJECT TITLE :Distributed Feature Selection for Efficient Economic Big Data Analysis - 2018ABSTRACT:With the rapidly increasing popularity of economic activities, a large amount of economic data is being collected. Although
PROJECT TITLE :Efficient Wideband DOA Estimation Through Function Evaluation Techniques - 2018ABSTRACT:This Project presents an economical analysis methodology for the functions involved within the computation of direction-of-arrival
PROJECT TITLE :Efficient System Tracking With Decomposable Graph-Structured Inputs and Application to Adaptive Equalization With Cyclostationary Inputs - 2018ABSTRACT:This Project introduces the graph-structured recursive least
PROJECT TITLE :Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes - 2018ABSTRACT:List successive cancellation decoder (LSCD) architectures have been recently proposed for the decoding

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry