Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation - 2016


The limited write endurance is one amongst the main obstacles for section-change random access memory (PRAM)-based mostly main memory. Traditionally, wear-leveling (WL) techniques were proposed to boost its lifetime by balancing write traffic. But, these techniques do not concern the endurance variation in PRAM chips. When completely different PRAM cells have distinct endurance, balanced writes results in lifetime degradation thanks to the weakest cells. In this paper, we first outline a replacement metric-wear rate (i.e., writes/endurance) considering both the write traffic and endurance distribution from application and hardware, respectively. When investigating the writing behavior of applications and endurance variation, we propose an design-level leveling mechanism to balance wear rate of cells across the PRAM chip. Hardware and algorithm to support the proposed leveling mechanism are presented. Moreover, there's an vital tradeoff between endurance improvement and swapping information volume. To co-optimize endurance and swapping, this case is formulated as a maximum weight excellent matching drawback in bipartite graph. Thereafter, a unique algorithm that minimizes wear-rate and swapping by using Kuhn-Munkras algorithm is proposed to maximise PRAM lifetime and minimize performance degradation. The experimental results show ~17× lifetime improvement over previous WL.

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