Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier - 2016


This paper presents an area-efficient low-power design for configurable booth multiplier. It's synthesized and post-layout simulated using ninety nm CMOS process and it occupies 951one µm2 and consumes 1.seventy three mW at 167 MHz. Comparatively, the proposed multiplier design requires forty three.12p.c and seventy five.sixty fivepercent lower space and power, respectively, compared with the state of the art work.

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