Floating-Point Butterfly Architecture Based on Binary SignedDigit Representation - 2016


Fast Fourier transform (FFT) coprocessor, having a vital impact on the performance of communication systems, has been a hot topic of research for several years. The FFT operate consists of consecutive multiply add operations over complicated numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become a lot of standard recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP issues (e.g., scaling and overflow/underflow). But, the main downside of FP butterfly is its slowness compared with its fixed-point counterpart. This reveals the motivation to develop a high-speed FP butterfly architecture to mitigate FP slowness. This temporary proposes a fast FP butterfly unit employing a devised FP fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on binary-signed-digit (BSD) representation. The FP 3-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and employed in the three-operand adder and also the parallel BSD multiplier therefore as to boost the speed of the FDPA unit. Moreover, changed Booth encoding is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is abundant faster than previous counterparts however at the cost of additional area.

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