Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm - 2017 PROJECT TITLE :Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm - 2017ABSTRACT:CORDIC algorithm is suitable to implement sine/cosine operate, however the massive variety of iterations cause great delay and overhead. Moreover, because of finite bit-width of operands and variety of iterations, the relative error of floating-purpose sine or cosine is terrible when the input angle is shut to 0 or p/a pair of, respectively. To overcome these shortcomings, TCORDIC algorithm, that combines low latency CORDIC and Taylor algorithm, is presented. Once analyzing the latency of ancient CORDIC, low latency CORDIC is proposed, which adopts the technique of sign prediction, compressive iterations, and parallel iterations. Besides, the calculating boundary (N), which is used for determining whether Taylor algorithm is selected or not in TCORDIC algorithm, is evaluated to achieve a trade-off between area and delay. Truncated multipliers are used to reduce the area further. Finally, Using TCORDIC algorithm, pipelined and iterative structures are implemented for IEEE-754 double precision floating-point sine/cosine with the input Z?[0, p/a pair of]. Under typical condition (1V, 25 °C), our styles are synthesized with 40 nm commonplace cell library. For a pipelined structure, the frequency is up to one.seventy GHz and area 194049.64 µm a pair of . Frequency decreases to one.45 GHz for iterative structure, but the world requires only 110590.81 µm 2 . TCORDIC is efficient in controlling relative error, and achieves the accuracy within one ulp (unit in the last place) for floating-point sine/cosine operate. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A Structured Visual approach to GALS Modelling and Verification of Communication Circuits - 2017 Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression - 2017