Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m) - 2016


This study presents the design and implementation of an efficient structure for fault tolerant bit-parallel polynomial basis multiplication and squaring over GF(2m), based mostly on the same strategy of Roving methodology with a minimum overhead. The Roving technique is an economical method for the circuits in that several similar and independent structures exist. The architectures of the polynomial basis multiplication and squaring over binary finite fields have inherent regularity in their subsections of the structures. Thus, they are compatible to the applied version of Roving fault tolerant method. To generalise the proposed design, the multiplication and squaring operations are examined for various primitive polynomial, as well as general irreducible polynomials, irreducible pentanomials and irreducible trinomials. In the proposed style, the extracted common circuit has low hardware utilisation compared with that of the most circuit. The fault tolerant circuit is constructed by using three copies of the common circuit, a comparator and a voter circuit. The comparator and voter have parallel architectures with low critical path delays, which is a essential issue in any highly computational system. The look has been successfully verified and synthesised onVirtex-four XC4VLX20zero FPGA using Xilinx ISE 11. The results show an overall improvement in the speed and hardware usage compared with those of previous styles.

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