High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes - 2017 PROJECT TITLE :High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes - 2017ABSTRACT:A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of 3 totally different binary coded decimal (BCD) codes, particularly the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and also the BCD-4221/5211 code. The signed-digit radix-ten recoding is employed to recode the BCD multiplier to the digit set [-five, five] from [0, nine]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples during a carry-free manner. The XS-three coded partial product (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). During this paper, an everyday decimal PPR tree using ODDS and BCD-4221/521one codes is proposed; it consists of a binary PPR tree block, a non-fastened size BCD-4221 counter block and a BCD-4221/521one PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-choose decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the forty five nm technology show that the proposed decimal multipliers are faster and need less hardware space than previous designs found within the technical literature. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2017 Logic Synthesis in Reversible PLA - 2016
