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1 |
A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory - 2016 |
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2 |
A Low Power Reconfigurable LFSR - 2016 |
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3 |
A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits - 2016 |
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4 |
An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA - 2016 |
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5 |
Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone Based Crossover - 2016 |
Abstract
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6 |
Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2016 |
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7 |
Design of Efficient BCD Adders in Quantum Dot Cellular Automata - 2016 |
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8 |
Energy dissipation of quantum-dot cellular automata logic gates - 2016 |
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9 |
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device - 2016 |
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10 |
Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers - 2016 |
Abstract
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11 |
Logic Synthesis in Reversible PLA - 2016 |
Abstract
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