PROJECT TITLE :
Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach - 2016
Shifted polynomial basis (SPB) and generalized polynomial basis (GPB) are two economical bases of representation in binary extension fields, and are widely studied. In this paper, we tend to use the GPB formulation to derive a replacement modified SPB (MSPB) representation for arbitrary irreducible trinomials and pentanomials. It's shown that the basis conversion from the MSPB to the SPB for trinomials is free of hardware price. We tend to have shown that multiplication based on SPB and MSPB representations will build use of Toeplitz matrix-vector product (TMVP) formulation. The existing TMVP block recombination (TMVPBR) approach is employed here to derive an efficient k-partitioning TMVPBR decomposition for digit-serial double basis multiplication that may achieve subquadratic space complexity. From synthesis results, we have a tendency to have shown that the proposed multiplier has less space and less area-delay product compared with the existing digit-serial multipliers. We conjointly show that the proposed multiplier using k-partitioning TMVPBR decomposition will provide a better tradeoff between time and space complexities.
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