Area-Delay Efficient Binary Adders in QCA PROJECT TITLE : Area-Delay Efficient Binary Adders in QCA (2014) ABSTRACT : As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this brief, we propose a new adder that outperforms all state-of-the-art competitors and achieves the best area-delay tradeoff. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. The 64-bit version of the novel adder spans over 18.72 μ2 of active area and shows a delay of only nine clock cycles, that is just 36 clock phases. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Sharing Logic for Built-In Generation of Functional Broadside Tests Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States
