An Improved Signed Digit Representation Approach for Constant Vector Multiplication - 2016 PROJECT TITLE : An Improved Signed Digit Representation Approach for Constant Vector Multiplication - 2016 ABSTRACT: In this brief, the multiplier-free implementation of the constant vector multiplication is reexamined. A completely unique improved signed digit illustration technique is proposed to beat the two main drawbacks of the present multiplier-free techniques: one) computational redundancy and a couple of) circuit irregularity. The basic difference between the proposed technique and the existing multiplier-free techniques may be a novel optimization framework primarily based on vector decomposition. The constant vector is decomposed into 2 terms: a “public” vector and a “personal” matrix which carries with it the general public operations shared by all of the entries and also the private operations of every individual entry, respectively. In this manner, the overall information flow can be divided into 2 regular steps: multiplied by the “public” vector first and then by the “personal” matrix. The computational complexity reduction task is then achieved by minimizing the length of the “public” vector and the quantity of operations in the “personal” matrix. Experimental results demonstrate that the proposed technique outperforms the prevailing multiplier-free techniques in fewer operations and more regular circuit structure. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Matrix Algebra Vectors Canonical-Signed-Digit (CSD) Multiplier-Free Vector Multiplication Vlsi An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA - 2016 Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach - 2016
