Design of area-delay efficient adder based circuits in quantum dot cellular automata - 2016


Semiconductor trade has achieved almost exponential lowering in feature size and has no one hundredpercent resolution in leakage current in CMOS. To replace CMOS technology, researchers done at nanoscale in recent years. Among rising technologies, QCA plays an important role. QCA will implement digital circuits with high speed, small size and reduced power consumption. Our aim is on coming up with of different sorts of adder circuits in QCA. Objective: Our objective is to minimize the world, latency and conjointly the amount of cells in adder circuits in QCADesigner. Results: The proposed style reduces the number of cells and area compared with the out there structures. By using QCA cells, totally different sorts of adders were designed Then they were simulated using QCADESIGNER tool. The performance can be analysed with the quantity of clock cycles. Conclusion: Experimental results show that the performances of proposed style of adders are a lot of efficient than standard designs.

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