Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2015
Radiation-induced multiple bit upsets (MBUs) are a major reliability concern in nanoscale technology nodes. Occurrence of such errors in the configuration frames of a field-programmable gate array (FPGA) device permanently affects the functionality of the mapped design. Periodic configuration scrubbing combined with a coffee-price error correction scheme is an efficient approach to avoid such a permanent result. Existing techniques employ error correction codes with significantly high overhead to mitigate MBUs in configuration frames. In this project, we have a tendency to gift a coffee-price error-detection code to detect MBUs in configuration frames with a generic scrubbing theme to reconstruct the erroneous configuration frame based on the concept of erasure codes. The proposed theme does not require any modification to the FPGA architecture. Implementation of the proposed theme on a Xilinx Virtex-half-dozen FPGA device shows that the proposed theme can detect a hundredp.c of MBUs in the configuration frames with solely three.threepercent resource occupation, while the recovery time is comparable with the previous schemes.
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