Power Optimization of Communication System Using Clock Gating Technique - 2015
A power optimized communication system is proposed during this project with clock gating technique. The encoder decoder block and the converter circuits are designed using clock gating for power optimization without degrading the system performance. Unwanted switching activities can be a lot of reduced by using clock gating techniques and power saving can be done. Negative latch has been used to generate the gated clock that feeds into varied blocks. The RTL view of the communication system with gated clock is also generated for implementation in hardware. We have used 2 clocks of frequencies 20MHz and 200MHz. For these frequencies, the hierarchy total power is reduced by sixty eight.27p.c, the logic power is reduced by 53.thirty threepercent, the signal power is reduced by 75.67p.c and therefore the clock domain and on-chip powers are same as it's in the system without using gated clock. Verilog HDL has been used to implement the varied blocks and simulation done using ModelSim ten.3c. RTL implementation has been done using Xilinx ISE suite thirteen.four.
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