PROJECT TITLE:

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2015

ABSTRACT:

During this project, we gift a carry skip adder (CSKA) structure that includes a higher speed however lower energy consumption compared with the standard one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the standard CSKA (Conv-CSKA) structure. Also, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure might be realized with each mounted stage size and variable stage size styles, whereby the latter additional improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, that lowers the power consumption without significantly impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling more voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of different adders employing a 45-nm static CMOS technology for a wide range of provide voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and thirty eight% enhancements within the delay and energy, respectively, compared with those of the Conv-CSKA. As well, the ability-delay product was very cheap among the structures thought-about during this project, while its energy-delay product was virtually the identical as that of the Kogge-Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the ability consumption compared with the newest works during this field while having a moderately high speed.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


PROJECT TITLE :A Low-Power High-Speed Comparator for Precise Applications - 2018ABSTRACT:A coffee-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator furthermore as the latch
PROJECT TITLE :A Low-Power Yet High-Speed Configurable Adder for Approximate Computing - 2018ABSTRACT:Approximate computing is an efficient approach for error-tolerant applications as a result of it will trade off accuracy for
PROJECT TITLE :A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design - 2018ABSTRACT:Multiplication may be a key elementary perform for several error-tolerant applications. Approximate multiplication is taken
PROJECT TITLE :Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit - 2017ABSTRACT:In this paper, a hybrid one-bit full adder design using both complementary metal-oxide-semiconductor (CMOS) logic and
PROJECT TITLE :High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations - 2017ABSTRACT:Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to extend the system

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry