FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration - 2015
This work presents an FPGA based mostly scalable mounted purpose QRD design based mostly on Givens Rotation algorithm.The proposed QRD core utilizes an efficient pipelined and unfolded 2D MAC primarily based systolic array architecture with dynamic partial reconfiguration(DPR) capability. An improved LUT based Newton-Raphson methodology is proposed for locating sq. root and inverse sq. root which helps in reducing the realm by 71percent and latency by fifty%, whereas operating at a frequency 49% above the existing boundary cell architectures. The scalability of the QRD core is achieved using DPR which results in reduction in dynamic power and area utilization as compared to a static implementation. The proposed architecture is implemented on Xilinx Virtex-half dozen FPGA for any real matrices of size m × n where, four = n = 8 and m = n by dynamically inserting or removing the partial modules. The evaluation results shows reduction in latency, space and power as compared to CORDIC primarily based architectures. The proposed scalable QRD core is employed for implementing a high performance adaptive equalizer(QRD-RLS Algorithm) employed in mobile receiver's and therefore the analysis is done by transmitting BPSK symbols within the coaching mode.
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