FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers - 2015
Field programmable gate array (FPGA) is widely used for efficient hardware realization of digital signal processing (DSP) circuits and systems. Finite impulse response (FIR) filter is that the core of any DSP and communication systems. To enhance the performance of FIR filter, an economical multiplier is required. Wallace tree and Vedic multipliers are used in this project for the implementation of sequential and parallel microprogrammed FIR filter architectures. The designs are realized using Xilinx Virtex-5 FPGA. FPGA implementation results are presented and analyzed. Based on the implementation results, sequential FIR filter using Wallace tree multiplier/carry skip adder combination proves to be additional efficient as compared to alternative multiplier/adder combinations.
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