Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications - 2015 PROJECT TITLE: Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications - 2015 ABSTRACT: The want to support various Digital Signal Processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications typically extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for a few computational errors. Hence, improving the energy efficiency of multiplications is essential. During this transient, we have a tendency to propose multiplier architectures which will tradeoff computational accuracy with energy consumption at design time. Compared with a precise multiplier, the proposed multiplier will consume fifty eight% less energy/op with average computational error of ~one p.c. Finally, we tend to demonstrate that such a little computational error does not notably impact the quality of DSP and the accuracy of classification applications. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Design of low power and high speed Carry Select Adder using Brent Kung adder - 2015 FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers - 2015
