Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator


A tri-layer bus system-on-chip (SoC) and a butterfly-path accelerator are used to reinforce system-level performance in a sequential minimal optimisation learning core. The tri-layer bus architecture is used to obtain an adequate transfer rate. The butterfly-path accelerator conjointly uses symmetrical access to resolve bottlenecks during linear prediction cepstral coefficients extraction. This novel design increases speed and flexibility without substantially increasing space. For implementation in chip manufacturing, the SoC is synthesised, placed and routed using the TSMC ninety nm technology library. The die size is two.09 mm × 2.09 mm, and the ability consumption is 8.nine mW. Compared with the non-butterfly-path style, the simulation results show that the proposed design provides a 2.4-fold speed increase. Additionally, clock down-sampling and voltage scaling scale back the power consumed by the proposed chip by a factor of eight.5. The experimental results make sure the improved speed and power that are provided by the proposed architecture and methods.

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