A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

PROJECT TITLE :

A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

ABSTRACT:

A absolutely-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power offer rejection (PSR) is proposed to supply a clean supply for noise-sensitive building blocks in wideband Communication systems. With the proposed purpose-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architecture is proposed and verified during a 65 nm CMOS process. In comparison to different totally-integrated styles, the output pole is ready to be the dominant pole, and the internal poles are pushed to higher frequencies with solely 50 $murm A$ of total quiescent current. For a 1.a pair of V input voltage and one V output voltage, the measured undershoot and overshoot is only 43 mV and eighty two mV, respectively, for load transient of zero $murm A$ to 10 mA among edge times of 200 ps. It achieves a transient response time of 1.fifteen ns and also the figure-of-merit (FOM) of 5.seventy four ps. PSR is measured to be higher than $-$ 12 dB over the full spectrum (DC to 20 GHz tested). The prototype chip measures $260times 90 murm m^2$, together with 140 pF of stacked on-chip capacitors.

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