Digital VLSI architectures for beam-enhanced RF aperture arrays


Beam-enhanced digital aperture arrays use 2-D infinite-impulse-response (IIR) filters as a preprocessing stage for phased/timed-array beamformers to get lower facet-lobe levels without compromising the array size or the main-lobe selectivity. A digital terribly-large-scale integration architecture is proposed for beam-enhanced linear aperture arrays. The proposed design consists of four subsystems: two-D IIR prefiltering, beam steering via fast computation of filter coefficients, compensation for nonlinear part, and phased/timed-array beamforming. Systolic-array architectures are used for first- and second-order a pair of-D IIR prefiltering subsystems, including fast computation of filter coefficients. The trade-off thanks to the nonlinear phase response of the two-D IIR prefilter is partially compensated via quick Fourier remodel-based mostly complicated part rotations. Styles are implemented on a Xilinx Virtex-six XC6VLX240T field-programmable gate-array device and verified using on-chip hardware cosimulation. Field-programmable gate-array designs for each a pair of-D IIR prefiltering and filter coefficient computation are mapped to standard-cell application-specific integrated circuits in forty five nm complementary metal-oxide semiconductor technology up to the synthesis level with provide VDC = V. For a simulation having 64 antennas with binary section-shift keying modulation, the beam-enhanced aperture array provides higher than ten dB improvement in bit error rate versus signal-to-interference ratio performance compared to phased/timed-array beamforming.

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