A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply - 2017


This paper presents a brand new power-economical electrocardiogram acquisition system that uses a fully digital design to reduce the ability consumption and chip area. The proposed design is compatible with digital CMOS technology and is capable of operating with a low provide voltage of 0.five V. In this architecture, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive elements, such as ac coupling capacitors, are used. A moving average voltage-to-time converter is employed, that behaves rather than the LNA and antialiasing filter. A digital feedback loop is utilized to cancel the impact of the dc offset on the circuit, which eliminates the requirement for coupling capacitors. The circuit is implemented in 0.18-um CMOS process. The simulation results show that the front-end circuit consumes 274 nW of power.

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