On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices


Many recent advances in sparse coding led its wide adoption in Signal Processing, pattern classification, and object recognition applications. Even with improved performance in state-of-the-art algorithms and also the hardware platform of CPUs/GPUs, solving a sparse coding problem still requires expensive computations, making real-time giant-scale learning a very challenging drawback. During this paper, we tend to cooptimize algorithm, architecture, circuit, and device for real-time energy-efficient on-chip hardware acceleration of sparse coding. The principle of hardware acceleration is to acknowledge the properties of learning algorithms, which involve several parallel operations of knowledge fetch and matrix/vector multiplication/addition. These days's von Neumann architecture, however, isn't suitable for such parallelization, due to the separation of memory and the computing unit that produces sequential operations inevitable. Such principle drives both the selection of algorithms and the design evolution from CPU to CMOS application-specific integrated circuits (ASIC) to parallel architecture with resistive crosspoint array (PARCA) that we tend to propose. The CMOS ASIC scheme implements sparse coding with SRAM dictionaries and all-digital circuits, and PARCA employs resistive-RAM dictionaries with special browse and write circuits. We show that 65 nm implementation of the CMOS ASIC and PARCA scheme accelerates sparse coding computation by and , respectively, compared to software running on a eight-core CPU. Simulated power for each hardware schemes lie in the milli-Watt vary, creating it viable for portable single-chip learning applications.

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