An Experimentation Platform for On-Chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs


In this paper, we discuss the design of an experimentation platform aimed at prototyping low-cost analog neural networks for on-chip integration with analog/RF circuits. Our goal is to make the platform as modular as possible. The purpose of such an integration is to provide support for a variety of tasks, including trust and aging monitoring, self-testing, and self-tuning, all of which require the classification of analog measurements obtained from on-chip sensors. An important focus is placed on cost-effective implementation, as evidenced by the following characteristics of neural network circuits: 1) low energy and area budgets; 2) robust learning in the presence of analog inaccuracies; and 3) long-term retention of learned functionality. Our chip is made up of a reprogrammable array of synapses and neurons, each of which is able to function below the threshold and consumes less than one microwatt of power. Dual-mode weight storage is utilized by the synapse circuits. There is 1) a dynamic mode, which allows for rapid bidirectional weight updates while training, and 2) a nonvolatile mode, which allows for the long-term storage of learned functionality. In this paper, we discuss a robust learning strategy and evaluate the performance of the system on several benchmark problems. These problems include the XOR2-6 and two-spirals classification tasks.

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