Thwarting Scan Based Attacks on Secure-ICs With On-Chip Comparison - 2014
Hardware implementation of cryptographic algorithms is subject to various attacks. It's been previously demonstrated that scan chains introduced for hardware testability open a back door to potential attacks. Here, we have a tendency to propose a scan-protection scheme that gives testing facilities each at production time and over the course of the circuit's life. The underlying principles to scan-in both input vectors and expected responses and to check expected and actual responses at intervals the circuit. Compared to regular scan tests, this technique has no impact on the quality of the test or the model-primarily based fault diagnosis. It entails negligible space overhead and avoids the employment of an authentication check mechanism.
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