Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies


As chip technologies scale down in size, one high-energy ion strike often affects multiple adjacent logic nodes. The thus-known as pulse quenching result, induced by single-event charge sharing collection, has been widely explored in efforts to find mitigation techniques for single-event transients (SETs) or single-event upsets (SEUs), and the dummy gate isolation has been proven to be an economical layout technique for pulse quenching enhancement. In this paper, the characterization of SET pulse quenching among dummy gate isolated logic nodes is performed in sixty five nm twin-well and triple-well CMOS technologies. Four groups of significant ion experiments are explored for the characterization, and the heart beat quenching impact is quantitatively analyzed well. The heartbeat quenching effects show different characteristics in twin-well and triple-well CMOS technologies.

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