Statistical Framework and Built-In Self Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators - 2016

PROJECT TITLE :

Statistical Framework and Built-In Self Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators - 2016

ABSTRACT:

This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip's maximum operating speed. This learned model will be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning methodology will avoid the utilization of applying any functional take a look at and, hence, lead to a third-order take a look at time reduction with a limited portion of chips placed into a slower bin compared with the traditional practical-test binning. This paper further presents a unique built-in self-speed-binning system, that embeds the learned chip-speed model with a engineered-in circuit such that the chip speed can be directly calculated on-chip without inquiring any offline ATE software, achieving a fourth-order test-time reduction compared with the standard speed binning. The experiments were conducted based mostly on 360 take a look at chips of a twenty eight-nm, 0.9 V, 1.six-GHz mobile-application system-on-chip.

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