High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations - 2017


Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to extend the system throughput, the parallelization of LFSR is usually needed. Previously, a method named state-area transformation was presented to cut back the complexity of parallel LFSR architectures. Exhaustive searches are performed to find sensible transformation matrix candidates. This transient proposes a replacement technique for construction of the transformation matrix together with a additional economical looking algorithm. The realization results indicate that the proposed architecture outperforms the previous arts, improving the hardware efficiency by around 35p.c and also the corresponding looking out algorithm finds the desirable transformation matrix abundant faster.

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