PROJECT TITLE :
Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM - 2017
This study presents a multi-level 2D discrete wavelet rework (DWT) architecture without off-chip RAM. Existing architectures use one off-chip RAM to store the image information, that increases the complexity of the system. For one-chip design, line-based design based on changed lifting theme is proposed. By replacing the multipliers with canonic sign digit multipliers, a critical path of one full-adder delay is achieved. As per theoretical estimate, for three-level 2D DWT with a picture of N × N size, the proposed architecture requires 123 adders, sixty six subtracters, 167 registers, temporal memory of seven.five N words and input RAM of 3 Nbytes. The estimated hardware demand shows that for the image size of 512 × 512 and three-level DWT, the proposed design involves a minimum of 14.1p.c less transistor-delay-product than existing architectures.
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