PROJECT TITLE :
Design and Applications of Approximate Circuits by Gate-Level Pruning - 2017
Energy-potency could be a crucial concern for several systems, starting from Internet of things objects and mobile devices to high-performance computers. Moreover, once forty years of prosperity, Moore's law is starting to point out its economic and technical limits. Noticing that several circuits are over-designed and that a lot of applications are error-resilient or need less precision than offered by the existing hardware, approximate computing has emerged as a potential answer to pursue enhancements of digital circuits. In this regard, a technique to systematically tradeoff accuracy in exchange for area, power, and delay savings in digital circuits is proposed: gate-level pruning (GLP). A CAD tool is build and integrated into a standard digital flow to offer a wide selection of price-accuracy tradeoffs for any typical style. The methodology is first demonstrated on adders, achieving up to seventy eightpercent energy-delay-area reduction for tenp.c mean relative error. It is then detailed how this methodology can be applied on a more advanced system composed of a multitude of arithmetic blocks and memory: the discrete cosine rework (DCT), which may be a key building block for image and video processing applications. Even though arithmetic circuits represent but fourpercent of the whole DCT space, it is shown that the GLP technique will cause twenty one% energy-delay-space savings over the complete system for a reasonable image quality loss of 24 dB. This vital saving is achieved thanks to the pruned arithmetic circuits, which sets some nodes at constant values, enabling the synthesis tool to any simplify the circuit and memory.
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