Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015


A brand new style theme meant to boost the performance of true single-part clocked (TSPC) twin modulus prescalers is presented. 2 branches of TSPC D flip-flops are merged to reduce each power and device count. An HSPICE simulation of the proposed scheme demonstrates the highest power potency and best power-delay product among the referenced designs.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE :Guest Editorial Special Issue on the 2015 IEEE International Instrumentation and Measurement Technology Conference Pisa, Italy, May 11–14, 2015ABSTRACT:The thirty second annual IEEE International Instrumentation
PROJECT TITLE :A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line ArchitectureABSTRACT:A 3 MHz-to-1.eight GHz, 94 μW-to-nine.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology
PROJECT TITLE :A Low-Power, Low-Cost Infra-Red Emitter in CMOS TechnologyABSTRACT:During this paper, we present the look and characterization of an occasional-power low-value infra-red emitter based on a tungsten micro-hotplate
PROJECT TITLE :A Low-Power, Dual-Wavelength Photoplethysmogram (PPG) SoC With Static and Time-Varying Interferer RemovalABSTRACT:This paper presents an occasional-power, reflectance-mode photoplethysmogram (PPG) front end with
PROJECT TITLE :Low-power, parasitic-insensitive interface circuit for capacitive microsensorsABSTRACT:Capacitive transduction is ubiquitously employed at macro- and particularly micro-scales because of their simple structure and

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry