Optimized Memristor-Based Multipliers - 2017

PROJECT TITLE :

Optimized Memristor-Based Multipliers - 2017

ABSTRACT:

Since memristors came to the forefront of research, minimal work has explored their application to pc arithmetic. This paper proposes 2 memristor-based implementations of an N-bit shift-and-add multiplier, one using IMPLY operations and a second using MAD operations. The optimized IMPLY-based mostly implementation reduces the baseline delay from 2N2 + 29N steps and 17N+3 memristors to 2N2 + 21N steps and 7N+1 memristors. A second implementation is proposed that's constructed from MAD gates, a lower-space, lower-delay various to IMPLY logic. This design performs an N-bit multiplication in N2 + N steps with 5N memristors and 3N+a pair of drivers. Both styles require fewer steps and but one/half dozen of the amount of components of a ancient CMOS design. Finally, both of the implementations are extended to implement radix-2 Booth multipliers. The IMPLY design solely will increase by 1 step per iteration and 2N memristors and drivers. The MAD style will increase by N memristors and 6N switches but maintains the same delay because the shift-and-add multiplier. Both designs maintain a lower area and lower delay than the CMOS equivalent.

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