Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits - 2017 PROJECT TITLE :Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits - 2017ABSTRACT:Silicon nanowire reconfigurable field impact transistors (SiNW RFETs) abolish the physical separation of n-sort and p-type transistors by absorbing both roles in a configurable approach within a doping-free technology. But, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so way. In this paper, we gift first steps to a brand new compact and economical design of combinational circuits by using transistor-level reconfiguration. We have a tendency to contribute new basic gates realized with silicon nanowires, like two/3-XOR and MUX gates. Exemplifying our approach with four-bit, 8-bit and sixteen-bit conditional carry adders, we were in a position to scale back the quantity of transistors to almost one [*fr1]. With our current case study we tend to show that SiNW technology can cut back the required chip area by sixteen despite larger size of the individual transistor, and improve circuit speed by twenty six%. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI HSPICE MTech Projects Optimized Memristor-Based Multipliers - 2017 Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops - 2017
