Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications - 2017


The restricted size and power budgets of area-bound systems usually contradict the necessities for reliable circuit operation inside high-radiation environments. In this paper, we have a tendency to propose the smallest resolution for soft-error tolerant embedded memory nonetheless to be presented. The proposed complementary twin-modular redundancy (CDMR) memory relies on a four-transistor dynamic memory core that internally stores complementary information values to supply an inherent per-bit error detection capability. By adding easy, low-overhead parity, miscalculation-correction capability is added to the memory design for strong soft-error protection. The proposed memory was implemented in a 65-nm CMOS technology, displaying as a lot of as a 3.five×1 smaller silicon footprint than other radiation-hardened bitcells. Yet, the CDMR memory consumes between forty eight% and eighty sevenpercent less standby power than other considered solutions across the entire operating region.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE : Enhanced Frequency Regulation Using Multilevel Energy Storage in Remote Area Power Supply Systems ABSTRACT: RAPS systems with a high percentage of renewable power generation require frequency assistance from
PROJECT TITLE :Energy-Efficient and Distributed Network Management Cost Minimization in Opportunistic Wireless Body Area Networks - 2018ABSTRACT:Mobility induced by limb/body movements in Wireless Body Space Networks (WBANs) considerably
PROJECT TITLE :Dynamic, Fine-Grained Data Plane Monitoring With Monocle - 2018ABSTRACT:Ensuring network reliability is important for satisfying service-level objectives. However, diagnosing network anomalies during a timely fashion
PROJECT TITLE :Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter - 2018ABSTRACT:This paper presents a new area and power efficient VLSI architecture for least-mean-sq. (LMS) adaptive
PROJECT TITLE :An Area Efficient 1024-Point Low Power Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators - 2018ABSTRACT:Radix-a pair of k delay feed-back and radix-K delay commutator are the foremost well-known

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry