PROJECT TITLE :
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications - 2017
The restricted size and power budgets of area-bound systems usually contradict the necessities for reliable circuit operation inside high-radiation environments. In this paper, we have a tendency to propose the smallest resolution for soft-error tolerant embedded memory nonetheless to be presented. The proposed complementary twin-modular redundancy (CDMR) memory relies on a four-transistor dynamic memory core that internally stores complementary information values to supply an inherent per-bit error detection capability. By adding easy, low-overhead parity, miscalculation-correction capability is added to the memory design for strong soft-error protection. The proposed memory was implemented in a 65-nm CMOS technology, displaying as a lot of as a 3.five×1 smaller silicon footprint than other radiation-hardened bitcells. Yet, the CDMR memory consumes between forty eight% and eighty sevenpercent less standby power than other considered solutions across the entire operating region.
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