Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding - 2017 PROJECT TITLE :Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding - 2017ABSTRACT:A replacement low-power (LP) scan-based mostly built-in self-check (BIST) technique is proposed based mostly on weighted pseudorandom check pattern generation and reseeding. A brand new LP scan design is proposed, which supports each pseudorandom testing and deterministic BIST. Throughout the pseudorandom testing section, an LP weighted random check pattern generation theme is proposed by disabling a part of scan chains. Throughout the deterministic BIST phase, the planning-for-testability architecture is changed slightly while the linear-feedback shift register is kept short. In each the cases, only a little range of scan chains are activated during a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST - 2017 A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices - 2017
