A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices - 2017


This temporary presents a completely unique 4096-point radix-four memory-based fast Fourier remodel (FFT). The proposed architecture follows a conflict-free strategy that solely needs a complete memory of size N and some additional multiplexers. The control is additionally simple, as it's generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to scale back the utilization of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is economical in terms of hardware resources, as is shown by the experimental results.

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