PROJECT TITLE :
Low-Power Parallel Chien Search ArchitectureUsing a Two-Step Approach - 2016
This transient proposes a brand new power-economical Chien search (CS) design for parallel Bose-Chaudhuri-Hocquenghem (BCH) codes. For syndrome-primarily based decoding, the CS plays a important role in finding error locations, however exhaustive computation incurs a huge waste of power consumption. In the proposed architecture, the searching process is decomposed into two steps primarily based on the binary matrix illustration. In contrast to the first step accessed every cycle, the second step is activated solely when the primary step is successful, resulting in remarkable power saving. Furthermore, an economical architecture is presented to avoid the delay increase in critical methods caused by the 2-step approach. Experimental results show that the proposed two-step design for the BCH (8752, 8192, forty) code saves power consumption by up to fifty% compared with the traditional architecture.
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