PROJECT TITLE :
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply - 2016
This paper presents a new power-economical electrocardiogram acquisition system that uses a totally digital architecture to reduce the power consumption and chip space. The proposed architecture is compatible with digital CMOS technology and is capable of operating with an occasional provide voltage of 0.five V. In this design, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive components, like ac coupling capacitors, are used. A moving average voltage-to-time converter is employed, which behaves instead of the LNA and antialiasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, that eliminates the need for coupling capacitors. The circuit is implemented in zero.eighteen-um CMOS process. The simulation results show that the front-end circuit consumes 274 nW of power.
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