Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units - 2016

PROJECT TITLE :

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units - 2016

ABSTRACT:

Split-radix fast Fourier transform (SRFFT) is a perfect candidate for the implementation of a coffee-power FFT processor, as a result of it's rock bottom variety of arithmetic operations among all the FFT algorithms. In the design of such processors, an economical addressing theme for FFT knowledge with twiddle factors is needed. The signal flow graph of SRFFT is the identical as radix-two FFT, and thus, the traditional address generation schemes of FFT information might conjointly be applied to SRFFT. However, SRFFT has irregular locations of twiddle factors and forbids the application of radix-2 address generation methods. This brief presents a shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by employing a changed radix-two butterfly unit. The butterfly unit exploits the multiplier-gating technique to save lots of dynamic power at the expense of using a lot of hardware resources. Additionally, 2 novel address generation algorithms for each the trivial and nontrivial twiddle factors are developed. Simulation results show that compared with the traditional radix-two shared-memory implementations, the proposed style achieves over twenty% lower power consumption when computing a 1024-purpose advanced-valued transform.

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