High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver - 2016 PROJECT TITLE : High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver - 2016 ABSTRACT: A Viterbi Decoder (VD) is employed to decode the convolutional codes, where convolutional codes are commonly used to encode digital information before transmission. However, there is a giant selection of modern wireless Communication standards; a versatile hardware platform which will be configured to support completely different standards remains required. During this paper, a reconfigurable Viterbi decoder has been designed. The proposed Viterbi decoder has an design that supports constraint lengths three, 5, and seven, and code rates 1/a pair of and 1/three which makes it compatible with several common standards, like Wi-Max, WLAN, 3GPP2, GSM and LTE. The proposed Viterbi decoder has been simulated using Xilinx ISE fourteen.five simulator and implemented with VHDL on Xilinx Zed board, Zynq-7000 FPGA using Xilinx iMPACT device configuration tool. Moreover, in the proposed design design, a modified add-compare-select unit that efficiently reduces power consumption by 26percent and space by 21p.c is employed. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Cellular Radio Radio Receivers Field Programmable Gate Arrays Hardware Description Languages Wireless Lan Wimax Convolutional Codes Long Term Evolution Telecommunication Standards Viterbi Decoding CWFP: Novel Collective Write back and Fill Policy for LastLevel DRAM Cache - 2016 Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes - 2016