PROJECT TITLE :
Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes - 2016
As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a growing interest on error correction codes that may correct multibit errors. Orthogonal Latin sq. (OLS) codes are an fascinating possibility thanks to their low-complexity decoding and modular construction. Several works have additionally shown that it is doable to improve OLS codes, for instance, by providing extra error correction for adjacent errors. In explicit, a method has been recently proposed to implement triple adjacent error correction (TAEC) on double error correction (DEC) OLS codes. That theme exploits the properties of OLS codes to achieve TAEC using an freelance error correction logic and will not require extra parity check bits. This could be useful as, in many cases, the errors caused by MCUs are adjacent. In this paper, a more economical technique to implement TAEC for DEC OLS codes is presented. The proposed method will be used as long as there are sufficient parity check bits to interleave among the information bits. This can be the case for DEC OLS codes of up to 64 bits, which can be used to guard sixteen- and sixty four-bit knowledge words. The new scheme uses an optimized bit placement that interleaves information and parity check bits to simplify the decoding. In specific, correction of single, double, and triple adjacent errors is now achieved with one circuit that is a minor modification of the quality OLS decoding. This reduces area, power, and delay, making the new theme attractive for circuit implementations.
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