An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA - 2016


A high performance substitution box (S-Box) FPGA implementation using Galois Field GF (28) is presented in this paper. An optimum variety of pipeline registers based mostly on Spartan-3E FPGA is addressed in this paper. The planning is absolutely synthesizable using Verilog and will simply be converted to ASIC implementation. Consequently, a fast and space efficient implementation of pipelined S-Box was synthesized and implemented using Xilinx ISE v13.4 and Xilinx Spartan-3E XC3S2500E-4 FPGA because the target device. Hardware testing was performed and the results were verified and located to be clone of simulation results. The applicable variety of pipeline stages is found to be two stages in terms of LUTs required and speed. The timing results from the 'Place and Route' report indicate that the utmost clock frequency which will be applied to the planning is 701.262MHz, with an output delay that's equal to a pair of clock cycles.

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