An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Codes Decoding - 2016

PROJECT TITLE :

An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Codes Decoding - 2016

ABSTRACT:

In numerous memory and Communication systems, Bose-Chaudhuri-Hocquenghem (BCH) codes are widely used to reinforce reliability. One-pass Chase soft-call decoding algorithm for BCH code was previously proposed to realize important performance improvement over traditional hard-call decoding while not increasing too much computational complexity. The bottleneck in a conventional one-pass Chase decoding is the procedure of judging whether or not an obtained error locator polynomial is valid. In this paper, a completely unique algorithm that may efficiently verify eligibility of each generated error locator polynomial is proposed. The downside is initial reformulated as a polynomial modulo drawback, where repeated squaring will be employed for more simplification. In order to decrease the vital path delay and hardware complexity, an economical polynomial division algorithm based mostly on polynomial inversion is also proposed. Further, a VLSI design for the proposed algorithm is presented. The implemented results show that the proposed eligibility checking algorithm reduces the gate counts to only twelve% of a typical polynomial selection algorithm without introducing any speed penalty. The projected area reduction achieved in an exceedingly complete one-pass Chase decoder is approximately seventy fivep.c. In addition, post-layout simulation shows that the proposed algorithm is twenty times a lot of power-efficient than the traditional method.

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