Trigger-Centric Loop Mapping on CGRAs - 2016

PROJECT TITLE :

Trigger-Centric Loop Mapping on CGRAs - 2016

ABSTRACT:

A coarse-grained reconfigurable architecture (CGRA) is a promising platform based mostly on issues for each performance and power potency. One in all the primary obstacles that CGRAs would possibly face is a way to accelerate loops with if-then-else (ITE) structures. A recent management paradigm for CGRAs named triggered instruction architecture (TIA) will give an efficient scheme to accelerate loops with ITE structures. Nonetheless common loop mapping frameworks cannot leverage this scheme autonomously. To this end, this transient makes two contributions: 1) identify and remove redundancy nodes from a knowledge flow graph and a couple of) propose an integrated approach-TRMap, which consists of operations merging, Boolean operations offloading, and transformation of triggers. Our experimental results from some very important kernels extracted from SPEC2006 benchmarks and Digital Signal Processing applications show that by using TIA theme, TRMap is able to accelerate loops with ITE structures to an execution that's 1.38× and 1.sixty four× faster than that achieved by a full predication scheme (FP-Choi) and a state-of-the-art method (BRMap).

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