Network-on-Chip for Turbo Decoders - 2016 PROJECT TITLE : Network-on-Chip for Turbo Decoders - 2016 ABSTRACT: The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This temporary proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and also the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based mostly on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure provides an improvement of 53% for HSDPA and thirteen3p.c for LTE in throughput/space efficiency compared with state-of-the-art NoC solutions. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Vlsi Decoding 3G Mobile Communication Access Protocols Long Term Evolution Network-On-Chip Turbo Codes Network-On-Chip (NOC) Turbo Decoder A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm - 2016 Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation - 2016