Network-on-Chip for Turbo Decoders - 2016


The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This temporary proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and also the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based mostly on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure provides an improvement of 53% for HSDPA and thirteen3p.c for LTE in throughput/space efficiency compared with state-of-the-art NoC solutions.

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