A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator - 2017 PROJECT TITLE :A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator - 2017ABSTRACT:This paper presents a two.5D integrated microprocessor die, memory die, and accelerator die with two.5D silicon interposer I/Os. The utilization of such two.5D silicon interposer I/Os give a scalable interconnection for core-core (up to thirty two cores), core-memory (four× storage capacity) and core-accelerator (4.four× speedup in H.264 decoder). The two.5D integrated chip was implemented in GF 65 nm process with multicore microprocessor operated at 500 MHz under 1.two V supply with 1.08 W power dissipation. A try of 8 Gbps 2.5D silicon interposer I/O is designed for each of twelve inter-die Communication channels, achieving a bandwidth of 24 GBps with seven.5 pJ/bit energy efficiency. As a result, the desired applications like H.264 video knowledge analytics and AES encryption can achieve vital performance improvement of throughput and energy potency. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A Custom Accelerator for Homomorphic Encryption Applications - 2017 Overloaded CDMA Crossbar for Network-On-Chip - 2017