A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm - 2016

PROJECT TITLE :

A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm - 2016

ABSTRACT:

Video display systems embrace frame memory, that stores video information for show. To scale back system price, video information are typically compressed for storage in frame memory. A fascinating characteristic for show memory compression is support for the raster-scan processing order and also the fastened target compression ratio. Set partitioning in hierarchical trees (SPIHT) is an economical two-dimensional compression algorithm that guarantees a fastened target compression ratio, but its one-dimensional (1D) variation has received very little attention, while its 1D nature supports the raster-scan processing order. This paper proposes a unique hardware style for 1D SPIHT. The algorithm is changed to take advantage of parallelism for effective hardware implementation. For the encoder, dependences that prohibit parallel execution are resolved and a pipelined schedule is proposed. For the parallel execution of the decoder, the algorithm is changed to enable estimation of the bitstream length of each pass previous to decoding. This modification allows parallel and pipelined decoding operations, resulting in a high-throughput style for each encoder and decoder. Although the modifications slightly decrease compression efficiency, additional optimizations are proposed to boost such efficiency. As a result, the height signal-to-noise ratio drop is reduced from one.40 dB to 0.forty four dB. The throughputs of the proposed encoder and decoder are seven.04 Gbps and seven.63 Gbps, respectively, and their respective gate counts are thirty seven.a pair of K and 54.one K.

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