PROJECT TITLE :
Overloaded CDMA Crossbar for Network-On-Chip - 2017
On-chip interconnects are the performance bottleneck in fashionable system-on-chips. Code-division multiple access (CDMA) has been proposed to implement on-chip crossbars because of its fastened latency, reduced arbitration overhead, and higher bandwidth. In CDMA, medium sharing is enabled within the code house by assigning a restricted number of N-chip length orthogonal spreading codes to the processing elements sharing the interconnect. In this paper, we tend to advance overloaded CDMA interconnect (OCI) to boost the capacity of CDMA network-on-chip (NoC) crossbars by increasing the quantity of usable spreading codes. Serial and parallel OCI architecture variants are presented to adhere to totally different area, delay, and power requirements. Compared with the standard CDMA crossbar, on a Xilinx Artix-7 AC701 FPGA kit, the serial OCI crossbar achieves a hundredpercent higher bandwidth, 31p.c less resource utilization, and 45percent power saving, while the parallel OCI crossbar achieves N times higher bandwidth compared with the serial OCI crossbar at the expense of increased area and power consumption. A sixty five-node OCI-based mostly star NoC is implemented, evaluated, and compared with the same space division multiple access primarily based torus NoC for various synthetic traffic patterns. The analysis leads to terms of the resource utilization and throughput highlight the OCI as a promising technology to implement the physical layer of NoC routers.
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